Known CMOS shift register circuits require, to operate properly, two complementary clock signals. Shift registers include a series of "pass gates" through which data bits are conducted, or passed. Conventional CMOS pass gates consist of a PMOS transistor and an NMOS transistor with their drains and sources tied together. One of the two clock signals drives the gate of the PMOS transistor and the other clock signal drives the gate of the NMOS transistor.
For a gate to pass a data bit, both its transistors must be turned on. In order to turn on, the PMOS transistor requires a low clock signal and the NMOS transistor requires a high clock signal. Accordingly, the clock signal driving the PMOS transistor must be 180.degree. out of phase with the clock signal driving the NMOS transistor. If the two clock signals are not precisely 180.degree. out of phase the gate transistors may not turn on together, and thus, the gate may not pass a particular bit value at the desired frequency.
As discussed in more detail below, known CMOS shift registers include a number of pass gates connected in series, with adjacent gates connected by circuitry which essentially holds a passed bit value. The gates are grouped in pairs to form a series of "cells." A "shift" of a shift register consists of passing a bit from one cell to the next.
The gates in a cell are arranged such that the first gate conducts during a first portion of a clock cycle and the second gate conducts during a second portion of the clock cycle. For example, a cell may be arranged with the PMO transistor of the first gate driven by one of the clock signals and the PMOS transistor of the second gate driven by the second, or complementary, clock signal. Accordingly, a bit is shifted from one cell to the next in one full clock cycle.
CMOS shift register circuits typically include clock generation and compensation circuitry to ensure that the two clock signals remain 180.degree. out of phase at all points along the clock lines. As the speeds at which shift registers operate increase, and accordingly the clock rates increase, it becomes more and more important to keep the two required clock signals precisely 180.degree. out of phase, or complementary, at all points along the routed clock lines. Otherwise, the clock signals may drive the gate transistors of adjacent cells to turn on simultaneously, and thus, the pass gates may not properly sequence bit values.
The clock signals must also have fast edge rates to prevent successive pass gates from conducting at the same time. For example, a gate driven by low clock and high complementary clock signals must turn off before the next gate, which is driven by high clock and low complementary clock signals, turns on. If these gates are simultaneously conducting, a bit value passed through the first gate may continue through the second gate. The bit is then essentially lost because it is in the wrong register position. As the clock speeds increase, it is more and more difficult to keep the two required clock signals, with their fast edge rates, precisely 180.degree. out of phase.